
module test;
reg clock = 0;
  /* make a reset . */
  reg reset = 0;
  reg enable=0;
  wire [3:0] counter_out;
  initial begin
    $display ("time\t clk reset enable counter");
    $monitor ("%g\t %b   %b     %b      %b", 
	  $time, clock, reset, enable, counter_out );
    
    //reset=0;
    //enable=0;
    
  #5 reset = 1;    // Assert the reset
  #10 reset = 0;   // De-assert the reset
  #10 enable = 1;  // Assert enable
  #170 enable = 0; // De-assert enable
  #5 $stop;      // Terminate simulation
end


  /* Make a regular pulsing clock. */
 
  always #5 clock = !clock;

  //wire [3:0] value;
  counter c1 (clock, reset,enable,counter_out);

  
endmodule // module test ends